Cadence Design Systems Case Studies UPEK and Cadence: Enhancing Design Efficiency with Assertion-Based Verification Methodology

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	UPEK and Cadence: Enhancing Design Efficiency with Assertion-Based Verification Methodology Cadence Design Systems

UPEK and Cadence: Enhancing Design Efficiency with Assertion-Based Verification Methodology

Cadence Design Systems

Technology Category	Sensors - Flow Meters Sensors - Liquid Detection Sensors
Applicable Industries	National Security & Defense
Applicable Functions	Product Research & Development Quality Assurance
Use Cases	Virtual Reality Visual Quality Detection
Services	Testing & Certification
Challenge	UPEK, a California-based pioneer in biometric fingerprint technology, faced a significant challenge in its design and verification process. The company's design team was responsible for both design and verification elements of the flow, necessitating a high degree of flexibility to accommodate multiple interfaces across diverse computing systems. The primary business challenge was to provide customers with a faster time to market. To achieve this, UPEK needed to speed up the design cycle and incorporate an assertion-based verification methodology into its existing design and verification flow. Read More
About Customer	UPEK, Inc., based in California, is a pioneer in the field of biometric fingerprint technology. Since its inception in 1996, UPEK has been committed to making security simple and accessible. The company's solutions cater to a wide range of clients, from large federal agencies to individual personal computer users. In an era where mobile devices can easily access personal data, UPEK's innovative security solutions have become increasingly relevant and essential. The company's design team is responsible for both the design and verification elements of the flow, requiring a high degree of adaptability to integrate with multiple interfaces in diverse computing systems. Read More
Solution	To address these challenges, UPEK decided to incorporate an assertion-based verification methodology into its existing design and verification flow. The company utilized Cadence's Incisive Formal Verifier and Engineering Services to streamline the process. The Incisive Formal Verifier, combined with the Incisive Design Team Simulator, provided a complementary set of technologies that were effective at different points of the design and verification flow. Formal analysis was ideal for the early stages and complex-control logic, while simulation was applied for chip-level, end-to-end validation. The solution also included unified parsers, common language support, and an integrated debug environment to ensure ease-of-use. Read More Log in to view content
Contents

Technology Category

Sensors - Flow Meters

Sensors - Liquid Detection Sensors

Applicable Industries

National Security & Defense

Applicable Functions

Product Research & Development

Quality Assurance

Use Cases

Virtual Reality

Visual Quality Detection

Services

Testing & Certification

Challenge

UPEK, a California-based pioneer in biometric fingerprint technology, faced a significant challenge in its design and verification process. The company's design team was responsible for both design and verification elements of the flow, necessitating a high degree of flexibility to accommodate multiple interfaces across diverse computing systems. The primary business challenge was to provide customers with a faster time to market. To achieve this, UPEK needed to speed up the design cycle and incorporate an assertion-based verification methodology into its existing design and verification flow.

About Customer

UPEK, Inc., based in California, is a pioneer in the field of biometric fingerprint technology. Since its inception in 1996, UPEK has been committed to making security simple and accessible. The company's solutions cater to a wide range of clients, from large federal agencies to individual personal computer users. In an era where mobile devices can easily access personal data, UPEK's innovative security solutions have become increasingly relevant and essential. The company's design team is responsible for both the design and verification elements of the flow, requiring a high degree of adaptability to integrate with multiple interfaces in diverse computing systems.

Solution

To address these challenges, UPEK decided to incorporate an assertion-based verification methodology into its existing design and verification flow. The company utilized Cadence's Incisive Formal Verifier and Engineering Services to streamline the process. The Incisive Formal Verifier, combined with the Incisive Design Team Simulator, provided a complementary set of technologies that were effective at different points of the design and verification flow. Formal analysis was ideal for the early stages and complex-control logic, while simulation was applied for chip-level, end-to-end validation. The solution also included unified parsers, common language support, and an integrated debug environment to ensure ease-of-use.

Impact #1	The implementation of the assertion-based verification methodology had immediate positive effects for UPEK. The design team was able to quickly adapt to the new methodology, largely due to the automation features provided by Cadence's solutions. This new verification environment allowed the team to achieve their overall design quality goals more quickly and work with greater confidence. The early success experienced by the UPEK design team through the addition of formal verification to its design process resulted in time savings and improved quality on the first design.

Impact #1

The implementation of the assertion-based verification methodology had immediate positive effects for UPEK. The design team was able to quickly adapt to the new methodology, largely due to the automation features provided by Cadence's solutions. This new verification environment allowed the team to achieve their overall design quality goals more quickly and work with greater confidence. The early success experienced by the UPEK design team through the addition of formal verification to its design process resulted in time savings and improved quality on the first design.

Benefit #1	Sped up the design cycle by addressing key verification issues upfront in the design
Benefit #2	Increased efficiency and quality of the existing flow

Benefit #1

Sped up the design cycle by addressing key verification issues upfront in the design

Benefit #2

Increased efficiency and quality of the existing flow

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Overview

UPEK and Cadence: Enhancing Design Efficiency with Assertion-Based Verification Methodology

Operational Impact

Quantitative Benefit