Cadence Design Systems Case Studies IBM and Cadence: Streamlining Mainframe Computer Designs with Complex PCB Systems

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	IBM and Cadence: Streamlining Mainframe Computer Designs with Complex PCB Systems Cadence Design Systems

IBM and Cadence: Streamlining Mainframe Computer Designs with Complex PCB Systems

Cadence Design Systems

Technology Category	Processors & Edge Intelligence - Microcontrollers & Printed Circuit Boards Sensors - Temperature Sensors
Applicable Functions	Product Research & Development
Use Cases	Manufacturing Process Simulation Time Sensitive Networking
Services	Hardware Design & Engineering Services System Integration
Challenge	IBM, a leader in mainframe computing, was facing challenges in designing highly complex printed circuit boards (PCBs) for their mainframe computers. These PCBs, measuring as large as 50cm x 60cm, carry tens of thousands of signal interconnects in more than 10 layers of circuitry, with pin counts reaching 5,000 per component and more than 5,000 connections at the board level. The complexity of these designs made traditional schematics cumbersome and time-consuming to work with and analyze. IBM attempted to simplify the process by developing a solution based on entering the design attributes of each signal in a table or spreadsheet format. However, this added another step in the process as engineers had to convert the information into Hardware Description Language (HDL) to interface with the design platform. Additionally, analog elements could not be treated in this way and had to be configured manually. Read More
About Customer	IBM has been a leading player in mainframe computing for over 50 years. The company is known for its large-scale designs, creating mainframe computers that employ highly complex printed circuit boards (PCBs). These PCBs are enormous configurations of super-miniaturized components, with a single board carrying tens of thousands of signal interconnects in more than 10 layers of circuitry. The complexity of these designs, with pin counts reaching 5,000 per component and more than 5,000 connections at the board level, presents significant design challenges. Despite these challenges, IBM continues to innovate and lead the way in mainframe computing. Read More
Solution	IBM R&D Lab Germany adopted Cadence's Allegro System Architect GXL, an integrated solution that managed both tabular and schematic data in a full design and simulation environment. This solution allowed designers to enter and manipulate signal specifications as easily as with an accounting spreadsheet, reducing the input time to one-tenth of the time required to work directly with schematics, and with fewer errors. The solution also enabled rapid compilations, reducing the design code compilation time from 8-10 hours to a matter of seconds. This allowed for quick detection of errors and increased efficiency and productivity. The integrated environment of Allegro System Architect GXL also allowed engineers to assess more quickly and easily how front-end definitions would affect back-end design issues, reducing the time required for PCB development by 80%. Read More Log in to view content
Contents

Technology Category

Processors & Edge Intelligence - Microcontrollers & Printed Circuit Boards

Sensors - Temperature Sensors

Applicable Functions

Product Research & Development

Use Cases

Manufacturing Process Simulation

Time Sensitive Networking

Services

Hardware Design & Engineering Services

System Integration

Challenge

IBM, a leader in mainframe computing, was facing challenges in designing highly complex printed circuit boards (PCBs) for their mainframe computers. These PCBs, measuring as large as 50cm x 60cm, carry tens of thousands of signal interconnects in more than 10 layers of circuitry, with pin counts reaching 5,000 per component and more than 5,000 connections at the board level. The complexity of these designs made traditional schematics cumbersome and time-consuming to work with and analyze. IBM attempted to simplify the process by developing a solution based on entering the design attributes of each signal in a table or spreadsheet format. However, this added another step in the process as engineers had to convert the information into Hardware Description Language (HDL) to interface with the design platform. Additionally, analog elements could not be treated in this way and had to be configured manually.

About Customer

IBM has been a leading player in mainframe computing for over 50 years. The company is known for its large-scale designs, creating mainframe computers that employ highly complex printed circuit boards (PCBs). These PCBs are enormous configurations of super-miniaturized components, with a single board carrying tens of thousands of signal interconnects in more than 10 layers of circuitry. The complexity of these designs, with pin counts reaching 5,000 per component and more than 5,000 connections at the board level, presents significant design challenges. Despite these challenges, IBM continues to innovate and lead the way in mainframe computing.

Solution

IBM R&D Lab Germany adopted Cadence's Allegro System Architect GXL, an integrated solution that managed both tabular and schematic data in a full design and simulation environment. This solution allowed designers to enter and manipulate signal specifications as easily as with an accounting spreadsheet, reducing the input time to one-tenth of the time required to work directly with schematics, and with fewer errors. The solution also enabled rapid compilations, reducing the design code compilation time from 8-10 hours to a matter of seconds. This allowed for quick detection of errors and increased efficiency and productivity. The integrated environment of Allegro System Architect GXL also allowed engineers to assess more quickly and easily how front-end definitions would affect back-end design issues, reducing the time required for PCB development by 80%.

Impact #1	The adoption of Cadence's Allegro System Architect GXL by IBM R&D Lab Germany resulted in a streamlined design process for their highly complex PCBs. The solution's ability to manage both tabular and schematic data in a full design and simulation environment simplified the design process, reducing errors and increasing efficiency. The rapid compilation feature of the solution allowed for quick detection of errors, significantly increasing productivity. The integrated environment also provided a comprehensive view of the system structure and greater visibility of the buses, enabling better forecasting of the number of layers required. This holistic approach to design also allowed design teams to explore design alternatives, reducing the cost of experimentation and innovation, and resulting in the best-possible design.

Impact #1

The adoption of Cadence's Allegro System Architect GXL by IBM R&D Lab Germany resulted in a streamlined design process for their highly complex PCBs. The solution's ability to manage both tabular and schematic data in a full design and simulation environment simplified the design process, reducing errors and increasing efficiency. The rapid compilation feature of the solution allowed for quick detection of errors, significantly increasing productivity. The integrated environment also provided a comprehensive view of the system structure and greater visibility of the buses, enabling better forecasting of the number of layers required. This holistic approach to design also allowed design teams to explore design alternatives, reducing the cost of experimentation and innovation, and resulting in the best-possible design.

Benefit #1	Design teams using the tabular input capability of Allegro System Architect can complete the input in one-tenth of the time required to work directly with schematics.
Benefit #2	Compilation of the design code takes a fraction of time previously required for schematics, reducing from 8-10 hours to a matter of seconds.
Benefit #3	The integrated environment of Allegro System Architect GXL reduced the time required for PCB development by 80%.

Benefit #1

Design teams using the tabular input capability of Allegro System Architect can complete the input in one-tenth of the time required to work directly with schematics.

Benefit #2

Compilation of the design code takes a fraction of time previously required for schematics, reducing from 8-10 hours to a matter of seconds.

Benefit #3

The integrated environment of Allegro System Architect GXL reduced the time required for PCB development by 80%.

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Overview

IBM and Cadence: Streamlining Mainframe Computer Designs with Complex PCB Systems

Operational Impact

Quantitative Benefit