Cadence Design Systems
Case Studies
Freescale Semiconductor's Transition to UVM-MS for Enhanced Verification Efficiency
Overview
Freescale Semiconductor's Transition to UVM-MS for Enhanced Verification EfficiencyCadence Design Systems |
Analytics & Modeling - Digital Twin / Simulation Sensors - Temperature Sensors | |
Automotive Semiconductors | |
Product Research & Development Quality Assurance | |
Manufacturing Process Simulation Virtual Reality | |
System Integration Testing & Certification | |
Operational Impact
The transition to UVM and the implementation of a digital-centric verification environment resulted in a significant improvement in Freescale Semiconductor's verification process. The new methodology was quickly adopted by the company's analog designers, who could continue to develop directed tests using mixed-signal configurations in SPICE/behavior Verilog-AMS abstraction. Design verification engineers could complement top-level verification with UVM-powered constrained random stimulus using wreal configurations. The new methodology not only fostered 2X better productivity at the top level for both analog and digital verification engineers but also significantly reduced the verification effort for derivative products. The company achieved better coverage and improved detection of hard-to-find bugs, enhancing the overall quality and reliability of their products. | |
Quantitative Benefit
Significantly faster top-level verification of mixed-signal SoCs using wreal configurations | |
2X more verification productivity for digital and analog engineers achieved through rapid simulation launch and re-invoke | |
Improved coverage and traceability with Incisive vManager solution | |