Cadence Design Systems Case Studies Accelerating Network Switch Design: A Case Study of QLogic and Cadence

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	Accelerating Network Switch Design: A Case Study of QLogic and Cadence Cadence Design Systems

Accelerating Network Switch Design: A Case Study of QLogic and Cadence

Cadence Design Systems

Technology Category	Networks & Connectivity - Ethernet Processors & Edge Intelligence - System on a Chip
Applicable Functions	Product Research & Development Quality Assurance
Use Cases	Time Sensitive Networking
Services	System Integration
Challenge	QLogic, a leader in converged networking, enterprise Ethernet, and storage area networking (SAN) products, was faced with the challenge of quickly producing a sophisticated new network switch to capture market share. The company needed to consistently deliver technologies that transform data centers and storage networks globally. The challenge was to speed up the design and verification of a complex new network switch, a multi-million-gate system on chip (SoC), to drive scalable, non-blocking switch architectures across various protocols required from data center-class switching solutions. The complexity of the new design and the need to simulate the full ASIC before tapeout added to the challenge. Read More
About Customer	QLogic is a leading provider of converged networking, enterprise Ethernet, and storage area networking (SAN) products. The company uses a flex-port architecture in its application-specific integrated circuits (ASICs) to provide end-to-end, integrated solutions that address the broad networking spectrum. QLogic manufactures Fibre Channel and Ethernet converged networking solutions for successful integration into data centers. These switches provide the port-density and performance required to drive storage and data networks of leading original equipment manufacturers (OEMs) and end users worldwide. To continue expanding its market share, QLogic consistently delivers technologies that transform data centers and storage networks globally. Read More
Solution	To meet its stringent time-to-market requirements for the network switch, QLogic turned to the Cadence Palladium XP Verification Computing Platform. The platform supports design configurations up to 2 billion gates, delivering performance up to 4MHz and simultaneously supporting up to 512 users. It unifies simulation, acceleration, and emulation capabilities in a single environment, enabling efficient hardware/software system co-verification. QLogic used the platform to simultaneously explore the complex interaction of buses, ports, and crossbars at the system level. The company leveraged the capacity, speed, and debugging capabilities of Palladium XP to reduce the verification time associated with its latest ASIC design. Palladium XP also provided the capacity required for QLogic to create a synthesizable testbench, incorporating testbench parameters into read-only memory (ROM) for advanced system-level testing. Read More Log in to view content
Contents

Technology Category

Networks & Connectivity - Ethernet

Processors & Edge Intelligence - System on a Chip

Applicable Functions

Product Research & Development

Quality Assurance

Use Cases

Time Sensitive Networking

Services

System Integration

Challenge

QLogic, a leader in converged networking, enterprise Ethernet, and storage area networking (SAN) products, was faced with the challenge of quickly producing a sophisticated new network switch to capture market share. The company needed to consistently deliver technologies that transform data centers and storage networks globally. The challenge was to speed up the design and verification of a complex new network switch, a multi-million-gate system on chip (SoC), to drive scalable, non-blocking switch architectures across various protocols required from data center-class switching solutions. The complexity of the new design and the need to simulate the full ASIC before tapeout added to the challenge.

About Customer

QLogic is a leading provider of converged networking, enterprise Ethernet, and storage area networking (SAN) products. The company uses a flex-port architecture in its application-specific integrated circuits (ASICs) to provide end-to-end, integrated solutions that address the broad networking spectrum. QLogic manufactures Fibre Channel and Ethernet converged networking solutions for successful integration into data centers. These switches provide the port-density and performance required to drive storage and data networks of leading original equipment manufacturers (OEMs) and end users worldwide. To continue expanding its market share, QLogic consistently delivers technologies that transform data centers and storage networks globally.

Solution

To meet its stringent time-to-market requirements for the network switch, QLogic turned to the Cadence Palladium XP Verification Computing Platform. The platform supports design configurations up to 2 billion gates, delivering performance up to 4MHz and simultaneously supporting up to 512 users. It unifies simulation, acceleration, and emulation capabilities in a single environment, enabling efficient hardware/software system co-verification. QLogic used the platform to simultaneously explore the complex interaction of buses, ports, and crossbars at the system level. The company leveraged the capacity, speed, and debugging capabilities of Palladium XP to reduce the verification time associated with its latest ASIC design. Palladium XP also provided the capacity required for QLogic to create a synthesizable testbench, incorporating testbench parameters into read-only memory (ROM) for advanced system-level testing.

Impact #1	The use of Cadence Palladium XP Verification Computing Platform enabled QLogic to dramatically reduce the design and verification time on its complex new network switch. The platform's capacity, speed, and debugging capabilities were instrumental in achieving this. The transition from Palladium II to XP was fast, painless, and problem-free, thanks to the great support staff from Cadence. The platform also provided the capacity required for QLogic to create a synthesizable testbench, allowing the company to incorporate testbench parameters into read-only memory (ROM) for advanced system-level testing. This highly scalable system easily accommodated the QLogic multi-million-gate design, while giving the company room to grow for next-generation designs.

Impact #1

The use of Cadence Palladium XP Verification Computing Platform enabled QLogic to dramatically reduce the design and verification time on its complex new network switch. The platform's capacity, speed, and debugging capabilities were instrumental in achieving this. The transition from Palladium II to XP was fast, painless, and problem-free, thanks to the great support staff from Cadence. The platform also provided the capacity required for QLogic to create a synthesizable testbench, allowing the company to incorporate testbench parameters into read-only memory (ROM) for advanced system-level testing. This highly scalable system easily accommodated the QLogic multi-million-gate design, while giving the company room to grow for next-generation designs.

Benefit #1	Achieved verification of an ASIC design at the system level, earlier in the design cycle and faster than in previous ASIC verification projects
Benefit #2	Reduced verification time by 50% compared to previous, less-complex switches
Benefit #3	Palladium XP supports design configurations up to 2 billion gates, delivering performance up to 4MHz and simultaneously supporting up to 512 users

Benefit #1

Achieved verification of an ASIC design at the system level, earlier in the design cycle and faster than in previous ASIC verification projects

Benefit #2

Reduced verification time by 50% compared to previous, less-complex switches

Benefit #3

Palladium XP supports design configurations up to 2 billion gates, delivering performance up to 4MHz and simultaneously supporting up to 512 users

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Overview

Accelerating Network Switch Design: A Case Study of QLogic and Cadence

Operational Impact

Quantitative Benefit